Skip to main content

SemiSaga.com

Science & Technology Blog

Search This Blog

Home
About
Bus / Protocol
UVM
SystemVerilog
CMOS VLSI
Digital System Design
Electronics and Programming
Videos
FPGA
Electrical Engineering
RF Design

Posts

The most commonly used IC: 555 Timer

Posted by SemiSaga on August 30, 2020

Get link
Facebook
X
Pinterest
Email
Other Apps

Intro to FPGA development using: the Elbert V2

Posted by SemiSaga on July 26, 2020

Get link
Facebook
X
Pinterest
Email
Other Apps

UVM: TLM Example (running a test simulation)

Posted by SemiSaga on May 15, 2020

Get link
Facebook
X
Pinterest
Email
Other Apps

UVM: TLM Interfaces (Ports, Exports, FIFOs)

Posted by SemiSaga on May 10, 2020

Get link
Facebook
X
Pinterest
Email
Other Apps

Reviewing ICs

Posted by SemiSaga on April 16, 2020

Get link
Facebook
X
Pinterest
Email
Other Apps

Harmonic Distortion in non-linear RF Systems

Posted by SemiSaga on March 01, 2020

Get link
Facebook
X
Pinterest
Email
Other Apps

MOS Calculations Example

Posted by SemiSaga on February 23, 2020

Get link
Facebook
X
Pinterest
Email
Other Apps

Ads

Archive

July 20251
June 20252
September 20244
August 20244
July 20241
April 20241
February 20241
November 20221
May 20221
November 20201

August 20201
July 20201
May 20202
April 20201
March 20201
February 20202
January 20201
December 20192
November 201910
October 20199
September 20198
July 20192
June 20193
May 20191
April 20191
February 20192
January 20192
December 20181
November 20185

Show more Show less

Labels

Automation
bitcoin
blockchain
cmos
crypto
Electronics
fabrication
IT
mining
processors

Python
vlsi

Show more Show less

Report Abuse

Popular Posts

PCIe - TLP Header, Packet Formats, Address Translation, Config Space, Command Register, Configuration types

TLP Packet Format: FIG: TLP Packet Format. The Transaction Layer Packet Format is defined as: Starts with a Prefix, which is an optional one and, TLP Header and then, With/Without Data Payload, At the end of TLP Packet a TLP Digest, The information in TLP Packet Format is distributed as: TLP Prefixes. Header (mandatory). Data (included when applicable): depends on the transaction type. TLP Digest (optional). FIG: TLP Byte Information TLP Header: Provides Format of the packet. Type of the packet. Length of associated data, if available. Transaction Descriptor. Address/Routing information Byte enables Message encoding Completion Status FIG: Common TLP Header. 32-bit if information. Provides: Format, TLP Packet Type, Traffic Class info, Attributes, T Heads (Presence of TLP Prefix, if present), TLP Digest, End Point (TLP is Normal or Poisoned), Address Translation (When memory is available). Length (Data Length notation denoted in 32bit words) F...

Electronics Fundamentals: Oscilloscope-101

A Digital Oscilloscope is a multi-functional instrument for displaying, analyzing, and storing electrical signals. It is an indispensable tool for designing, manufacturing, and maintaining electronic equipment. Generating First Waveform on your Oscilloscope : FIG: Sine Wave (1ms/div) FIG: Single Cycle Waveform (100us/div) - Power-ON Function Generator and, Connect BNC-BNC cable from its Output-1 to CH-1 (channel-1) of the Oscilloscope. - Set V (peak to peak) = 1Vpp - Set Frequency output = 1kHz FIG: Adjustment knobs - Use Horizontal and Vertical knobs to adjust the signal - Set trigger level on the waveform to stabilize the signal - As you can see - 1kHz frequency is a low frequency, thus Time-base needs to be set to at least 1ms: Scale of 1kHz Frequency under a vibration microscope - What's the Physics behind this small frequency? Below are two microscope “slides”: a 1 kHz vibration and a 50 MHz vibration, each captured with an identical 2 GSa/s “optical sensor.” The dots are AD...

Blockchain, Mining, and Processors - Cryptocurrency Fundamentals

Cryptocurrency: Cryptocurrency , a medium of exchange, is a 'Blockchain-based' technology, which literally means it is based on 'Blocks'. They are all stored in a blockchain where each blockchain has its own digital coin. These Blocks are packages that carry permanently recorded data. The most popular example is Bitcoin. As a transaction occurs, the information for each transaction is collected and then validated by the network. This data will eventually reach a predetermined size, and then will be combined into a 'Block'. As these blocks are created they do not stand solo - they become linked with the other blocks to form a chain [= blockchain] . Synonyms of a Cryptocurrency: Digital Tokens, Tokens, Digital Assets, Digital Currency, Virtual Currency, Crypto Coins, Digital Coins, etc. Each crypto type has its own property and function. It is unlike a traditional currency - backed by a physical commodity such as gold or silver, or a Fiat currency like the U.S. D...

PCIe - Terminology, Throughput, Root Complex, End Point and, Switch

In my previous post, I introduced the topology and architecture of PCIe. After a careful study, I have gathered a detailed understanding of its terminology and working. Let's have a look! FIG: Various PCIe slots on a motherboard- PCIe x 4; 16; 1; 16; Conventional 5V 32Bit PCI, respectively. Source: Wikipedia Terminology: FIG: PCIe link between two devices consisting of one or more lane. Source: Wikipedia Switch, n-point, root complex can be directly connected with the PCIe Link. Link contains high-speed serial standard bus, which has a differential signaling. Diffrential signaling are software interrupts sent to a program to indicate an important event like user requests or illegal memory access errors (One transmit pin having two pairs of wires: Transmit +ve and -ve which increases noise immunity). *You can use kill -l on your linux/unix system to view the supported signals. For example: If +ve is affected with noise, and in a similar manner if -ve also gets ...

PCI Configuration Space Registers (Type 0 / Type 1)

PCI Configuration Space Type 0 is for PCI devices and, for Endpoints in case of PCIe. Type 1 Config Space is for PCI host controller and, for PCI Root Complex in case of PCIe. Type 0/1 Configuration Space: FIG: Config Space. The Config Space registers are common for both type 0/1. Device ID and Vendor ID: Identify the particular device. Status register: Provides error information, updated information, etc. Command register: Controls Bus Master and different utilities. Class code: Provides category of the device (Host Controller, IDE Bridge, SATA Controller, Ethernet Controller, etc). Revision ID of PCI. BIST - Built-In Self Test. Header Type Specific area is defined by Header type (0 or 1). Cache Line Size. Table: Configuration Space Registers. Table: Command Register Table: Status Register FIG: Type 0 Configuration Space Table: TYPE 0 Registers FIG: PCIe TYPE 1 Configuration Space Table: TYPE 1 Configuration Space Registers

Digital Electronics: Timing Diagrams

Timing Diagrams are graphs of digital signals as a function of time. Square Wave featuring Rise-Time and Fall-Time. Using the 50% Mark to measure the delays: In the above image, X-Axis: Time, Y-Axis: Voltage or the Signal. For example, let us ask ourselves what is the delay from S1 to S2? So, the frame of reference, in general, is the 50% mark of the rising-edge or the falling-edge to measure the time difference Δt = t2 - t1 . Have a common frame-of-reference. Conventions (Shown Below): *Different companies have a slightly different timing-diagram convention. Tri-State means the impedance is high (using Mega-ohms values). Asynchronous and Synchronous Timing Diagrams: Asynchronous Timing Diagram. Asynchronous TDs use combinatorial logic like Gates and Circuits without a clock. Output (Z) showing the propagation delay Tpd. Synchronous Timing Diagram. Devices and ICs like Microcontrollers, Microprocessors, Flip-Flops (single-b...

Digital Logic Systems - SSI, MSI, LSI, and VLSI (Basics)

DIGITAL Series - SSI / MSI / LSI / VLSI (Basics) Combinational Logic and SSI/MSI: Small Scale Integration and Medium Scale Integration - Glue of circuits. 3 variable Minterm possibilities (x, y, z): Notation - In the above table, the values are getting multiplied. The opposite of minterm is maxterm: Minterm - Sum of Minterms. Example: F(x, y, z) = SUMMATION m(6,7) Maxterm - Product of Sum. Example: F(x, y, z) = (x + y + z) * (/x + y + /z) *** Very Important Note - Karnaugh Maps (or K maps) are used for logical optimization but not included in this article. SSI / MSI Blocks: The present-day large scale integration few years ago, in today's time a small scale integration as shown on the following rough data. SSI → 10 to 100 MSI →100 to 1000 LSI → 1000 to 10,000 VLSI →10,000+ Transistor Count as per Moore's Law curve - Source: Wikipedia The highest transistor count as per current day (or...

Electronics Fundamentals: Oscilloscope-102 - Detailed Introduction, Types, Safety, Usage, History, Design Concept, MSO/DSO Working Principle

In the previous article on generating a sinusoidal waveform using an Oscilloscope, it was proposed that there are THREE fundamental steps on displaying, plotting, analyzing and stabilizing a waveform, which are the following basic Oscilloscope functions: Horizontal Vertical Trigger FIG: Lissajous Figures - source: wikipedia Now, lets ask some of the very basic questions in order to understand "Why Oscilloscope?" and the motivation behind its use in Electronics: NOTE - The topics and questions marked in color 'Blue' are covered to a certain extent in this post - i.e. 'Oscilloscope-102'. While, the topics covered in 'Red' are more covered in the section 'Oscilloscope-103' and 'Oscilloscope-104'. - Why do we use an Oscilloscope? Why NOT use something simple, like an Ammeter which measures Electric Current? [Using analog oscilloscope as an example.] - What is an Oscilloscope, an explanation? Types of Oscilloscopes? - Brief History, Impor...

System Verilog: Multiplexer

Fig: Multiplexer Multiplexer in digital circuit design is a circuit which selects one of its input by using the SELECT line. select[1:0] q 00 d[0] 01 d[1] 10 d[2] 11 d[3] FIG: 4 X 1 MUX. (Not Completely labeled); q1, q2, q3, q4 are the 4 outputs; a stands for and gate; o stands for or gate; n stands for not gate. SV Code (Gate-level model): module mux_gate_level( select, d, q ); input logic [1:0] select; input logic [3:0] d; output logic q; wire q1, q2, q3, q4; wire [1:0] SelectBar; not n1( SelectBar[0], select[0] ); not n2( SelectBar[1], select[1] ); and a1( q1, SelectBar[0], SelectBar[1], d[0] ); and a2( q2, select[0] , SelectBar[1], d[1] ); and a3( q3, SelectBar[0], select[1] , d[2] ); and a4( q4, select[0] , select[1] , d[3] ); or o1( q, q1, q2, q3, q4 ); endmodule SV C...

RF Chip Design: AC/DC Transistor Simulations using ADS (Keysight)

> In this post, we will discuss the details on how to simulate the AC circuits on ADS Keysight. AC Circuit Design: Connect a Resistor - R, and a Capacitor - C as shown below with AC simulation component. The start, stop, and step are described in the below image: To simulate the magnitude, you may use a rectangular plot as shown below: To add more rectangular plots such as dB, and phase, select and add using rectangular plot: To tune the plot by changing R and C values, use Tune functionality shown next to simulate option (shown below): Component selected - R Component selected - C Adjusting R and C values. You can observe the plot as it changes the magnitude, dB, and phase with respect to the frequency: RLC Simulation - Filter: At the resonance frequency, the capacitor and the inductor resonate, and the L-C combination of the circuit gets short-circuited thus the in is equal to out. In the circuit, Vac = polar (1, 0) V, where 1 = amplitude and 0= phase. Q = W * L ...

Powered by Blogger