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Electronics Fundamentals - Introduction to Resistors

Posted by SemiSaga on April 14, 2024

In the previous post we discussed about voltage, and current. In this post we will know more about the relationship between Voltage and Current i.e. Resist ors (unit s ymb ol: Ω or ohm ) - heart of electronics! The interesting I versus V characteristics that can be useful are: Resistors: I proportional to V Capacitors: I proportional to rate of change of V Diodes: I flows in one direction Thermistors: Temperature dependent resistors Photoresistors: Light dependent resistors Fig: Resistor. TYPES OF RESISTORS: > Wirewound Ceramic Power Resistors: Example Datasheet 1 20W vitreous enamel with leads ( view datasheet for more examples and types). 30W vitreous enamel 5W and 20W with mounting studs 20W Resistor with mounting studs > Wirewound Power Resistors: Example Datasheet 2 1W, 3W, and 5W axial ceramic 5W, 10W, and 25W conduction cooled / Dale-Type 50W conduction cooled (Dale-Type) > Carbon, Surface-Mount Resistors, and other types: 2W, 1W, 1/2W, 1/4W, and 1/8W Carbon compos

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Electronics Fundamentals - Voltage, Current

Posted by SemiSaga on February 04, 2024

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CMOS Microchip Design Fundamentals

Posted by SemiSaga on November 12, 2022

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Blockchain, Mining, and Processors - Cryptocurrency Fundamentals

Posted by SemiSaga on May 03, 2022

bitcoin blockchain crypto mining processors

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Build your fundamental Python concepts with these 5 Examples

Posted by SemiSaga on November 09, 2020

Automation Electronics IT Python

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The most commonly used IC: 555 Timer

Posted by SemiSaga on August 30, 2020

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Intro to FPGA development using: the Elbert V2

Posted by SemiSaga on July 26, 2020

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UVM: TLM Example (running a test simulation)

Posted by SemiSaga on May 15, 2020

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PCIe - TLP Header, Packet Formats, Address Translation, Config Space, Command Register, Configuration types

TLP Packet Format: FIG: TLP Packet Format. The Transaction Layer Packet Format is defined as: Starts with a Prefix, which is an optional one and, TLP Header and then, With/Without Data Payload, At the end of TLP Packet a TLP Digest, The information in TLP Packet Format is distributed as: TLP Prefixes. Header (mandatory). Data (included when applicable): depends on the transaction type. TLP Digest (optional). FIG: TLP Byte Information TLP Header: Provides Format of the packet. Type of the packet. Length of associated data, if available. Transaction Descriptor. Address/Routing information Byte enables Message encoding Completion Status FIG: Common TLP Header. 32-bit if information. Provides: Format, TLP Packet Type, Traffic Class info, Attributes, T Heads (Presence of TLP Prefix, if present), TLP Digest, End Point (TLP is Normal or Poisoned), Address Translation (When memory is available). Length (Data Length notation denoted in 32bit words) F

PCI Configuration Space Registers (Type 0 / Type 1)

PCI Configuration Space Type 0 is for PCI devices and, for Endpoints in case of PCIe. Type 1 Config Space is for PCI host controller and, for PCI Root Complex in case of PCIe. Type 0/1 Configuration Space: FIG: Config Space. The Config Space registers are common for both type 0/1. Device ID and Vendor ID: Identify the particular device. Status register: Provides error information, updated information, etc. Command register: Controls Bus Master and different utilities. Class code: Provides category of the device (Host Controller, IDE Bridge, SATA Controller, Ethernet Controller, etc). Revision ID of PCI. BIST - Built-In Self Test. Header Type Specific area is defined by Header type (0 or 1). Cache Line Size. Table: Configuration Space Registers. Table: Command Register Table: Status Register FIG: Type 0 Configuration Space Table: TYPE 0 Registers FIG: PCIe TYPE 1 Configuration Space Table: TYPE 1 Configuration Space Registers

PCIe - Terminology, Throughput, Root Complex, End Point and, Switch

In my previous post, I introduced the topology and architecture of PCIe. After a careful study, I have gathered a detailed understanding of its terminology and working. Let's have a look! FIG: Various PCIe slots on a motherboard- PCIe x 4; 16; 1; 16; Conventional 5V 32Bit PCI, respectively. Source: Wikipedia Terminology: FIG: PCIe link between two devices consisting of one or more lane. Source: Wikipedia Switch, n-point, root complex can be directly connected with the PCIe Link. Link contains high-speed serial standard bus, which has a differential signaling. Diffrential signaling are software interrupts sent to a program to indicate an important event like user requests or illegal memory access errors (One transmit pin having two pairs of wires: Transmit +ve and -ve which increases noise immunity). *You can use kill -l on your linux/unix system to view the supported signals. For example: If +ve is affected with noise, and in a similar manner if -ve also gets

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