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Showing posts from January, 2020

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A Powerful and Secondary Review: ASIC Design concepts

Posted by SemiSaga on January 12, 2020

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In my previous post, I introduced the topology and architecture of PCIe. After a careful study, I have gathered a detailed understanding of its terminology and working. Let's have a look! FIG: Various PCIe slots on a motherboard- PCIe x 4; 16; 1; 16; Conventional 5V 32Bit PCI, respectively. Source: Wikipedia Terminology: FIG: PCIe link between two devices consisting of one or more lane. Source: Wikipedia Switch, n-point, root complex can be directly connected with the PCIe Link. Link contains high-speed serial standard bus, which has a differential signaling. Diffrential signaling are software interrupts sent to a program to indicate an important event like user requests or illegal memory access errors (One transmit pin having two pairs of wires: Transmit +ve and -ve which increases noise immunity). *You can use kill -l on your linux/unix system to view the supported signals. For example: If +ve is affected with noise, and in a similar manner if -ve also gets

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