### System Verilog: Multiplexer

 Fig: Multiplexer

• Multiplexer in digital circuit design is a circuit which selects one of its input by using the SELECT line.

 select[1:0] q 00 d[0] 01 d[1] 10 d[2] 11 d[3]

 FIG: 4 X 1 MUX. (Not Completely labeled); q1, q2, q3, q4 are the 4 outputs; a stands for and gate; o stands for or gate; n stands for not gate.

• SV Code (Gate-level model):

module mux_gate_level( select, d, q );

input logic [1:0] select;
input logic [3:0] d;
output logic q;

wire q1, q2, q3, q4;
wire [1:0] SelectBar;

not n1( SelectBar[0], select[0] );
not n2( SelectBar[1], select[1] );

and a1( q1, SelectBar[0], SelectBar[1], d[0] );
and a2( q2, select[0] , SelectBar[1], d[1] );
and a3( q3, SelectBar[0], select[1]   , d[2] );
and a4( q4, select[0] , select[1]   , d[3] );

or o1( q, q1, q2, q3, q4 );

endmodule

• SV Code (using assign statement):

//mux using assign statement

module mux1( select, d, q );
input logic [1:0] select;
input logic [3:0] d;
output logic   q;

assign q = d[select];

endmodule
• SV Code (using always statement):
//mux using always statement

module mux2( select, d, q );
input logic [1:0] select;
input logic [3:0] d;
output logic   q;

always @(d or select) begin
q = d[select];
end

endmodule
• SV Code (using if statement):
//mux using if statement

module mux3( select, d, q );

input logic [1:0] select;
input logic [3:0] d;
output logic   q;

always_comb begin
if( select == 0 ) begin
q = d[0];
end

if( select == 1 ) begin
q = d[1];
end

if( select == 2 ) begin
q = d[2];
end

if( select == 3 ) begin
q = d[3];
end
end

endmodule
• SV Code (using if-else statement):
//mux using if else statement

module mux4( select, d, q );

input logic [1:0] select;
input logic [3:0] d;
output logic   q;

always_comb begin
if( select == 0 ) begin
q = d[0];
end

else if( select == 1 ) begin
q = d[1];
end

else if( select == 2 ) begin
q = d[2];
end

else if( select == 3 ) begin
q = d[3];
end
end

endmodule
• SV Code (using case statement):
//mux using "case"

module mux5( select, d, q );
input logic [1:0] select;
input logic [3:0] d;
output logic      q;

always_comb begin
case( select )
0 : q = d[0];
1 : q = d[1];
2 : q = d[2];
3 : q = d[3];
endcase
end

endmodule
• SV Code (using conditional operator):
//mux using conditional operator "?"

module mux6( select, d, q );

input logic [1:0] select;
input logic [3:0] d;
output logic      q;

assign q = ( select == 0 )? d[0] : ( select == 1 )? d[1] : ( select == 2 )? d[2] : d[3];
//assign y = ( condition1===true ) ? exp1 : exp2 ;
//assign y = ( condition1===true ) ? exp1 : ( condition2===true ) ? exp2 : ( condition3===true ) ? exp3 ;

endmodule