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TLP Packet Format: FIG: TLP Packet Format. The Transaction Layer Packet Format is defined as: Starts with a Prefix, which is an optional one and, TLP Header and then, With/Without Data Payload, At the end of TLP Packet a TLP Digest, The information in TLP Packet Format is distributed as: TLP Prefixes. Header (mandatory). Data (included when applicable): depends on the transaction type. TLP Digest (optional). FIG: TLP Byte Information TLP Header: Provides Format of the packet. Type of the packet. Length of associated data, if available. Transaction Descriptor. Address/Routing information Byte enables Message encoding Completion Status FIG: Common TLP Header. 32-bit if information. Provides: Format, TLP Packet Type, Traffic Class info, Attributes, T Heads (Presence of TLP Prefix, if present), TLP Digest, End Point (TLP is Normal or Poisoned), Address Translation (When memory is available). Length (Data Length notation denoted in 32bit words) F...

PCI Configuration Space Registers (Type 0 / Type 1)

PCI Configuration Space Type 0 is for PCI devices and, for Endpoints in case of PCIe. Type 1 Config Space is for PCI host controller and, for PCI Root Complex in case of PCIe. Type 0/1 Configuration Space: FIG: Config Space. The Config Space registers are common for both type 0/1. Device ID and Vendor ID: Identify the particular device. Status register: Provides error information, updated information, etc. Command register: Controls Bus Master and different utilities. Class code: Provides category of the device (Host Controller, IDE Bridge, SATA Controller, Ethernet Controller, etc). Revision ID of PCI. BIST - Built-In Self Test. Header Type Specific area is defined by Header type (0 or 1). Cache Line Size. Table: Configuration Space Registers. Table: Command Register Table: Status Register FIG: Type 0 Configuration Space Table: TYPE 0 Registers FIG: PCIe TYPE 1 Configuration Space Table: TYPE 1 Configuration Space Registers

System Verilog: Multiplexer

Fig: Multiplexer Multiplexer in digital circuit design is a circuit which selects one of its input by using the SELECT line. select[1:0] q 00 d[0] 01 d[1] 10 d[2] 11 d[3] FIG: 4 X 1 MUX. (Not Completely labeled); q1, q2, q3, q4 are the 4 outputs; a stands for and gate; o stands for or gate; n stands for not gate. SV Code (Gate-level model): module mux_gate_level( select, d, q ); input logic [1:0] select; input logic [3:0] d; output logic q; wire q1, q2, q3, q4; wire [1:0] SelectBar; not n1( SelectBar[0], select[0] ); not n2( SelectBar[1], select[1] ); and a1( q1, SelectBar[0], SelectBar[1], d[0] ); and a2( q2, select[0] , SelectBar[1], d[1] ); and a3( q3, SelectBar[0], select[1] , d[2] ); and a4( q4, select[0] , select[1] , d[3] ); or o1( q, q1, q2, q3, q4 ); endmodule SV C...

RFIC Design: AC/DC Transistor Simulations using ADS (Keysight)

> In this post, we will discuss the details on how to simulate the AC circuits on ADS Keysight. AC Circuit Design: Connect a Resistor - R, and a Capacitor - C as shown below with AC simulation component. The start, stop, and step are described in the below image: To simulate the magnitude, you may use a rectangular plot as shown below: To add more rectangular plots such as dB, and phase, select and add using rectangular plot: To tune the plot by changing R and C values, use Tune functionality shown next to simulate option (shown below): Component selected - R Component selected - C Adjusting R and C values. You can observe the plot as it changes the magnitude, dB, and phase with respect to the frequency: RLC Simulation - Filter: At the resonance frequency, the capacitor and the inductor resonate, and the L-C combination of the circuit gets short-circuited thus the in is equal to out. In the circuit, Vac = polar (1, 0) V, where 1 = amplitude and 0= phase. Q = W * L ...

PCIe - Terminology, Throughput, Root Complex, End Point and, Switch

In my previous post, I introduced the topology and architecture of PCIe. After a careful study, I have gathered a detailed understanding of its terminology and working. Let's have a look! FIG: Various PCIe slots on a motherboard- PCIe x 4; 16; 1; 16; Conventional 5V 32Bit PCI, respectively. Source: Wikipedia Terminology: FIG: PCIe link between two devices consisting of one or more lane. Source: Wikipedia Switch, n-point, root complex can be directly connected with the PCIe Link. Link contains high-speed serial standard bus, which has a differential signaling. Diffrential signaling are software interrupts sent to a program to indicate an important event like user requests or illegal memory access errors (One transmit pin having two pairs of wires: Transmit +ve and -ve which increases noise immunity). *You can use kill -l on your linux/unix system to view the supported signals. For example: If +ve is affected with noise, and in a similar manner if -ve also gets ...

Fundamentals of Transistors (Part-1)

Transistor: Basic building blocks in all of the electronics. MOSFET Cross Sectional view: MOSFET Top view: Metal Oxide Semiconductor Field Effect Transistor. Fabricated on a p-type Silicon. n-channel transistor (shown above): Source (S) of charge carriers. Drain (D). Silicon Dioxide (SiO2) thin Gate in between: Applying enough voltage will turn-on the transistor. Top view, in the above figure, shows source and the drain on left and right, respectively. Gate in the middle. Current is proportional to the width - more width (W) = more current. Initial transistors were discrete, packaged up inside a package with a few leads, and electronic circuits were made using these (shown below). Initial Integrated Circuits were put into a single slab of silicon called a silicon chip, and wired. First chip example - Intel's 4004 microprocessor with 2300 transistors wired together (shown below). 4004 Image Courtesy - Intel. Considering the transistor as a black box with silicon inside it containing...

Electronics Fundamentals: All About Resistors (Part-1)

Image Courtesy: Data Sheet - Chip Resistors (Yageo / Farnell) As mentioned in previous post about series and parallel resistors, let us prove the formulas to begin with: If the Resistors R1 and R2 are connected in series , we can apply Kirchhoff's law here: V = V1 + V2, and V1 = IR1, V2 = IR2 => V = IR1 + IR2 = I (R1 + R2) => as per ohm's law, V = IR => IR = I (R1 + R2) OR R = R1 + R2, where R is the equivalent resistance for two resistors connected in series. Similarly, If two or more resistors are connected in parallel circuit assuming it is a closed circuit with equivalent current I, then current running through R1 is I1 and current through R2 is I2. Thus, I = I1 + I2 => V/R = V/R1 + V/R2 [as voltage remains the same across parallel resistance] OR 1/R = 1 / R1 + 1 / R2 * A popular "international" alternative notation replaces the decimal point with the unit multiplier, thus 4k7 or 1M0. A 2.2ohm resistor becomes 2R2. There is an analogous scheme fo...

PCIe - Layering

FIG: Open-end PCIe x1 for longer PCIe cards supported @ x1 Speeds. Source: Wikipedia Previously, I discussed the details of a PCIe switch and how it is used for address-based routing and how it is used to control the flow by maintaining the requests. To further this concept now I am going to discuss the PCIe to PCI/PCI-X Bridge. PCIe to PCI/PCI-X Bridge: It provides a connection between PCIe and PCI/PCI-X. If our system needs to be connected with the PCI devices, then we need this bridge which converts the high-speed serial bus of PCIe to the address and data multiplexed bus by using a bridge. PCI Compatible Model: It has the ability to calculate one by one and configure PCIe similar to PCI. Boots the existing OS without modifications. Existing I/O device drivers can be used without any modifications. Configure/enable PCIe functionality by PCI configurations. PCIe Layering: FIG: All PCI express Layers. PCIe is a packet-based commu...

RFIC Design: Transistor DC Simulations using ADS by Keysight

> To design the transistor dc schematic, we are using GPDK 180 nm library: Select 'nmosrf' from the palette, and select width to 5u (micron) Finger as shown below: Add technology netlist as it is necessary to simulate your circuit: Add DC simulation to ensure (shown below): Go to sources - freq. domain on left panel, and add DC voltage: Connect voltage source (-) to ground, and voltage source (+) to gate of nMOS. Name the gate input as 'G' as shown below: Ground the Source and Body as below. Connect the Drain with current probe, and ground the other end of ID - drain current probe. Edit Simulation Settings. Simulation Settings - Standard_ic. Naming Drain as D. Naming current probe as ID. Renaming drain-source voltage to VDS, and gate voltage to VB. Also, add variable as shown below: Add parameter sweep to add sweep and simulation variables for the rectangular simulation plot (shown below): Adding VDS to the plot (click and name x-axis as VDS which is already mention...

RFIC Design: DC Simulations using ADS by Keysight

*Disclaimer* - This article uses free licensed 30-day evaluation version of ADS by Keysight (courtesy). > Loading schematic to your workspace: If there is an existing schematic that you would like to load: Go to ADS (Main) screen. Click File > Open > select schematic available in your 'workspace_lib'. To add schematic to your workspace_lib folder, you may copy the schematic folder to your workspace_lib inside the workspace folder. If the Main ADS window does not show the schematic or output file, press F5 function key to Refresh. Example loaded Schematic (screen): Example loaded Result Display (screen): Loading PDK (Process Design Kit) - 180nm in this case to your ADS (free trial): ADS Main screen menu > manage libraries > Add Library Definition File > browse Folder of the available PDK > select 'lib.defs' Once the PDK library is selected, it will show all the transistor types, as shown in the below image: Use the 'Netlist include' to creat...

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