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Showing posts from September, 2024

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Fundamentals of Transistors (Part-1)

Posted by SemiSaga on September 22, 2024

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Electronics Fundamentals: All About Resistors (Part-1)

Posted by SemiSaga on September 22, 2024

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RF Chip Design: AC/DC Transistor Simulations using ADS (Keysight)

Posted by SemiSaga on September 17, 2024

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PCIe - TLP Header, Packet Formats, Address Translation, Config Space, Command Register, Configuration types

TLP Packet Format: FIG: TLP Packet Format. The Transaction Layer Packet Format is defined as: Starts with a Prefix, which is an optional one and, TLP Header and then, With/Without Data Payload, At the end of TLP Packet a TLP Digest, The information in TLP Packet Format is distributed as: TLP Prefixes. Header (mandatory). Data (included when applicable): depends on the transaction type. TLP Digest (optional). FIG: TLP Byte Information TLP Header: Provides Format of the packet. Type of the packet. Length of associated data, if available. Transaction Descriptor. Address/Routing information Byte enables Message encoding Completion Status FIG: Common TLP Header. 32-bit if information. Provides: Format, TLP Packet Type, Traffic Class info, Attributes, T Heads (Presence of TLP Prefix, if present), TLP Digest, End Point (TLP is Normal or Poisoned), Address Translation (When memory is available). Length (Data Length notation denoted in 32bit words) F...

PCI Configuration Space Registers (Type 0 / Type 1)

PCI Configuration Space Type 0 is for PCI devices and, for Endpoints in case of PCIe. Type 1 Config Space is for PCI host controller and, for PCI Root Complex in case of PCIe. Type 0/1 Configuration Space: FIG: Config Space. The Config Space registers are common for both type 0/1. Device ID and Vendor ID: Identify the particular device. Status register: Provides error information, updated information, etc. Command register: Controls Bus Master and different utilities. Class code: Provides category of the device (Host Controller, IDE Bridge, SATA Controller, Ethernet Controller, etc). Revision ID of PCI. BIST - Built-In Self Test. Header Type Specific area is defined by Header type (0 or 1). Cache Line Size. Table: Configuration Space Registers. Table: Command Register Table: Status Register FIG: Type 0 Configuration Space Table: TYPE 0 Registers FIG: PCIe TYPE 1 Configuration Space Table: TYPE 1 Configuration Space Registers

PCIe - Terminology, Throughput, Root Complex, End Point and, Switch

In my previous post, I introduced the topology and architecture of PCIe. After a careful study, I have gathered a detailed understanding of its terminology and working. Let's have a look! FIG: Various PCIe slots on a motherboard- PCIe x 4; 16; 1; 16; Conventional 5V 32Bit PCI, respectively. Source: Wikipedia Terminology: FIG: PCIe link between two devices consisting of one or more lane. Source: Wikipedia Switch, n-point, root complex can be directly connected with the PCIe Link. Link contains high-speed serial standard bus, which has a differential signaling. Diffrential signaling are software interrupts sent to a program to indicate an important event like user requests or illegal memory access errors (One transmit pin having two pairs of wires: Transmit +ve and -ve which increases noise immunity). *You can use kill -l on your linux/unix system to view the supported signals. For example: If +ve is affected with noise, and in a similar manner if -ve also gets ...

Electronics Fundamentals: Oscilloscope-103

What are the different types of Oscilloscopes? There’s mainly Real Time Oscilloscopes and Equivalent Time Based Oscilloscopes also known as sampling scopes. Real-time Scope: Real time Scope uses Horizontal scale to trigger and capture the desired waveform. Below shows the reconstructed waveform. Fig. 1. Real time Scope Waveform acquisition (Keysight) Real time scopes are very useful for: ● Non repetitive signals ● Able to display one-time transient events ● Large memory depth ● No external trigger needed Sampling Scopes: An equivalent time sampling oscilloscope, sometimes simply called a “sampling scope,” measures only the instantaneous amplitude of the waveform at the sampling instant. In contrast to the real-time scope, the input signal is only sampled once per trigger. The next time the scope is triggered, a ...

System Verilog: Multiplexer

Fig: Multiplexer Multiplexer in digital circuit design is a circuit which selects one of its input by using the SELECT line. select[1:0] q 00 d[0] 01 d[1] 10 d[2] 11 d[3] FIG: 4 X 1 MUX. (Not Completely labeled); q1, q2, q3, q4 are the 4 outputs; a stands for and gate; o stands for or gate; n stands for not gate. SV Code (Gate-level model): module mux_gate_level( select, d, q ); input logic [1:0] select; input logic [3:0] d; output logic q; wire q1, q2, q3, q4; wire [1:0] SelectBar; not n1( SelectBar[0], select[0] ); not n2( SelectBar[1], select[1] ); and a1( q1, SelectBar[0], SelectBar[1], d[0] ); and a2( q2, select[0] , SelectBar[1], d[1] ); and a3( q3, SelectBar[0], select[1] , d[2] ); and a4( q4, select[0] , select[1] , d[3] ); or o1( q, q1, q2, q3, q4 ); endmodule SV C...

Electronics Fundamentals: Oscilloscope-102 - Detailed Introduction, Types, Safety, Usage, History, Design Concept, MSO/DSO Working Principle

In the previous article on generating a sinusoidal waveform using an Oscilloscope, it was proposed that there are THREE fundamental steps on displaying, plotting, analyzing and stabilizing a waveform, which are the following basic Oscilloscope functions: Horizontal Vertical Trigger FIG: Lissajous Figures - source: wikipedia Now, lets ask some of the very basic questions in order to understand "Why Oscilloscope?" and the motivation behind its use in Electronics: NOTE - The topics and questions marked in color 'Blue' are covered to a certain extent in this post - i.e. 'Oscilloscope-102'. While, the topics covered in 'Red' are more covered in the section 'Oscilloscope-103' and 'Oscilloscope-104'. - Why do we use an Oscilloscope? Why NOT use something simple, like an Ammeter which measures Electric Current? [Using analog oscilloscope as an example.] - What is an Oscilloscope, an explanation? Types of Oscilloscopes? - Brief History, Impor...

RF Chip Design: AC/DC Transistor Simulations using ADS (Keysight)

> In this post, we will discuss the details on how to simulate the AC circuits on ADS Keysight. AC Circuit Design: Connect a Resistor - R, and a Capacitor - C as shown below with AC simulation component. The start, stop, and step are described in the below image: To simulate the magnitude, you may use a rectangular plot as shown below: To add more rectangular plots such as dB, and phase, select and add using rectangular plot: To tune the plot by changing R and C values, use Tune functionality shown next to simulate option (shown below): Component selected - R Component selected - C Adjusting R and C values. You can observe the plot as it changes the magnitude, dB, and phase with respect to the frequency: RLC Simulation - Filter: At the resonance frequency, the capacitor and the inductor resonate, and the L-C combination of the circuit gets short-circuited thus the in is equal to out. In the circuit, Vac = polar (1, 0) V, where 1 = amplitude and 0= phase. Q = W * L ...

Electronics Fundamentals: Oscilloscope-101

A Digital Oscilloscope is a multi-functional instrument for displaying, analyzing, and storing electrical signals. It is an indispensable tool for designing, manufacturing, and maintaining electronic equipment. Generating First Waveform on your Oscilloscope : FIG: Sine Wave (1ms/div) FIG: Single Cycle Waveform (100us/div) - Power-ON Function Generator and, Connect BNC-BNC cable from its Output-1 to CH-1 (channel-1) of the Oscilloscope. - Set V (peak to peak) = 1Vpp - Set Frequency output = 1kHz FIG: Adjustment knobs - Use Horizontal and Vertical knobs to adjust the signal - Set trigger level on the waveform to stabilize the signal - As you can see - 1kHz frequency is a low frequency, thus Time-base needs to be set to at least 1ms: Scale of 1kHz Frequency under a vibration microscope - What's the Physics behind this small frequency? Below are two microscope “slides”: a 1 kHz vibration and a 50 MHz vibration, each captured with an identical 2 GSa/s “optical sensor.” The dots are AD...

PCIe - Layering

FIG: Open-end PCIe x1 for longer PCIe cards supported @ x1 Speeds. Source: Wikipedia Previously, I discussed the details of a PCIe switch and how it is used for address-based routing and how it is used to control the flow by maintaining the requests. To further this concept now I am going to discuss the PCIe to PCI/PCI-X Bridge. PCIe to PCI/PCI-X Bridge: It provides a connection between PCIe and PCI/PCI-X. If our system needs to be connected with the PCI devices, then we need this bridge which converts the high-speed serial bus of PCIe to the address and data multiplexed bus by using a bridge. PCI Compatible Model: It has the ability to calculate one by one and configure PCIe similar to PCI. Boots the existing OS without modifications. Existing I/O device drivers can be used without any modifications. Configure/enable PCIe functionality by PCI configurations. PCIe Layering: FIG: All PCI express Layers. PCIe is a packet-based commu...

RTL Design and Verification of AXI Stream Master in Xilinx Vivado

Master AXI Stream Specification: FIG: AXI Stream Master RTL Schematic. Send user-provided data by AXI-Stream Protocol. User provides needed data to send to data input. When user activates send , the module should send user-provided data by AXI-Stream. Send is async signal. After finish sending should activate finish output for 1 cycle. Verilog Design Module: AXI Master (.v file) ---------------------------------------------------- module axi_stream_master(input areset_neg, aclk, send, input [31:0] data, input tready, output reg tvalid, output tlast, output reg [31:0] tdata, output reg finish //AXI Stream interface ); reg [31:0] data_buf; always@(posedge send or negedge areset_neg) if (~areset_neg) data_buf <= 0; else data_buf <= data; //when send goes HIGH, we //send the data info into the d...

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