*AXI4-Lite is the limited version of AXI4.

The AXI4-Lite interface is a subset of the AXI4 interface intended for communication with control registers in components.

The key features of the AXI4-Lite interface are:
  • All transactions are burst length of 1.
  • All data accesses are the same size as the width of the data bus.
  • Support for data bus width of 32-Bit or 64-Bit.
  • All accesses are equivalent to AWCACHE or ARCACHE equal to b0000.
  • Exclusive accesses are not supported.

AXI-Lite Channels:
  • Supports 2 main operations/transactions: Read and Write.
    • Read transaction:
      • Read the address channel (data is read from here).
      • Read the data channel.
Channel architecture of reads.
    • Write transaction:
      • Write the address channel (M Sends data to be written to S).
      • Write a data channel.
      • Write a response channel.
Channel architecture of writes.

Each of the five independent channels consists of a set of information signals and uses a two-way VALID and READY handshake mechanism.

Signal List of AXI-Lite: (source: arm's documentation)

Handshake Process:

  • All five channels use the same VALID/READY handshake to transfer data and control information.
  • Similar handshake mechanism like AXI-Stream.

To prevent a deadlock situation, you must observe the dependencies that exist between the handshake signals. In any transaction:
  • The TVALID signal of one AXI component must not be dependent on the READY signal of the other component in the transaction. > M
  • The READY signal can wait for assertion of the VALID signal. > S

Relationships between the channels:
  • The relationship between the address, read, write, and write response channels is flexible.
  • For example, the write data can appear at an interface before the write address that relates to it.
Two relationships that must be maintained are:
  • Read data must always follow the address to which the data relates.
  • A write response must always follow the last write transfer in the write transaction to which the write response relates.
Write Strobes:
  • When asserted, a write strobe indicates that the corresponding byte lane of the data bus contains valid information to be updated in memory.

There is one write strobe for each eight bits of the write data bus, so WSTRB[n] corresponds to WDATA[(8 x n) + 7: (8 x n)]. Figure below shows this relationship on a 64-bit data bus.

A master must ensure that the write strobe are asserted only for byte lanes that can contain valid data as determined be the control information for the transaction.

  • To support complex system designs, it is often necessary for both the interconnect and other devices in the system to provide protection against illegal transactions.
Table: 3-Bit Signal
[0] >  This is used be some masters to indicate their processing mode. A privileged processing mode typically has a  greater level of access within a system.

[1] > This is used in systems where a greater degree of differentiation between processing modes is required.

[2] > This bit gives an indication if the transaction is an instruction or a data access.

Response Signaling:
  • The AXI protocol allows response signaling for both read and write transactions.
  • For read transactions the response information from the slave is passed alongside the read data itself, however
  • for writes the response information is conveyed along the write response channel.
  • The AXI protocol responses are:
    • OKAY
    • EXOKAY (exclusive ok)
    • SLVERR (slave error)
    • DECERR (decode error)

  • This section describes the interoperability of AXI and AXI4-Lite Masters and Slaves.