- We will connect our designed AXI-Lite Master to AXI-Lite Slave Verification IP.
- Exchange the data between them.
- This Verification IP acts as both Master and Slave.
|FIG (ports): AXI Verification IP (Pass-Through).|
|FIG: AXI VIP Slave|
- The AXI Verification IP can be either: MASTER, PASS THROUGH (it connect AXI Slave to Master), or SLAVE.
- This Protocol is supported by AXI3, AXI4, and AXI4LITE (choose this in Customize IP).
- Modes: Read Only, Read Write, Write Only.
- AXI VIP Slave
- Structure: The AXI VIP Can be configured in three different modes.
- AXI master VIP
- AXI slave VIP
- AXI pass-through VIP
- SystemVerilog Interface is used to communicate with external Testbench.
- Protocol related things are generated using AXI Protocol Checker.
|Test Bench for AXI Slave VIP|
- Slave Agent: Agent of our Verification IP.
- TB is considered Static to a Virtual Interface.
- Interface: It is a SystemVerilog (SV) statement.
- It is an object which contains the module ports.
|AXI Slave VIP Agent Structure|
- The Agent consists of three main parts:
- Write Driver: writes to AXI-Lite.
- Read Driver: Supports the Read part of AXI-Lite.
- Monitor: Control, check, and generate ready protocol transactions.
- Virtual Interface: Connect static and dynamic worlds.
|FIG: Memory Model|
- The AXI-Lite can contain memory in it. The AXI Slave VIP has a simple memory model and it is an associative array of SystemVerilog.
- The write transaction can write to the memory model and the read transaction can read data from the memory.
- At the same time, the memory model has backdoor APIs for you to access memory directly, which are:
- backdoor_memory_write: writes data to memory
- backdoor_memory_read: reads data from memory
- While coding the test bench for the AXI VIP, the following requirements must be met. Else, the AXI does not work. Also, these are the requirements for all VIPs.
- Create a module test bench as all other standard SystemVerilog test benches.
- Import two required packages. axi_vip_pkg and <component_name>_pkg.
- The <component_name>_pkg includes agent classes and its subclasses for AXI VIP.
- Declare agents. One agent for one AXI VIP has to be declared.
Slave VIP without memory model
Slave VIP with memory model
Pass-through VIP without memory model
Pass-through VIP with memory model
agent = new("my VIP agent",<hierarchy_path>.IF);
Starting the VIP:
Example design is shown below:
|AXI Master VIP|
|AXI Pass-Through VIP|
|AXI Slave VIP|
|Simulated Waveform Output.|
- Monitor transactions between two AXI connections.
- Generate AXI transactions.
- Check for AXI protocol compliance.