Physical Design Flow - Overview


=> Floorplanning (Considering square shape chip for illustration):-

  • The above image shows how the way the core and die will look like.
  • Blue region: The area where the primary core logic defining the functionality and the netlist sets. 
  • White region: Defines the Die section.
  • The above figure shows the Preplaced Cells (Cells which have got certain functionality).
  • For Example, A - acts as an adder, B - acts as a multiplier, C - acts as a divider.
    • So all the pre-defined functions are already encapsulated in these blocks.
    • The location of preplaced cells is based on the complete connectivity of the netlist (where would they sit and do they access boundaries very often, and so on).

  • Surround preplaced cells with decoupling capacitors (shown in the below figure). Since, A, B, and C already have some internal logic (gates, FFs, clock cells, etc) so they might switch very rapidly. So when they switch logic, there might be a condition of huge current demand. So, this particular block should be able to suffice the power needs whenever there is a current demand while switching logic. Thus the capacitors get charged (from the power supply) - This concept is related to cross-talk.

  • Power Planning: Here we create a mesh. Instead of having one source of power supply we will be having multiple sources of power supply.

  • When there are 1000s of logics charging from 0 to 1 demanding current at the same time, the above grid structure helps.

  • After creating the above mesh structure, in and out pin placement needs to be done in the die area (not shown, think yourself?). Hint: Left side - input pins, Right side - output pins.

  • Finally, Logic Cell Placement Blockage needs to be done in between the Die and Core area to ensure that there will be no logic cells accidentally placed in this area. 


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