### Flip-Flops: RTL Design and Testbench in Verilog

D Flip Flop:
 FIG: RTL Schematic of a D-Flip Flop circuit.

Data Flow Modeling:

module dff_df(d,c, q,q1);
input d,c;
output q,q1;
wire x,y;
assign x = d&c;
assign y = ~d&c;
assign q = ~(x|q1);
assign q1 = ~(y|q);
endmodule

module dff_tb_v;

// Inputs
reg d;
reg c;

// Outputs
wire q;
wire q1;

// Instantiate the Unit Under Test (UUT)
dff_df uut (
.d(d),
.c(c),
.q(q),
.q1(q1)
);

initial begin
// Initialize Inputs
d = 0;
c = 0;

// Wait 100 ns for global reset to finish
#100;
d=0; c=1;
#100;
d=1; c=0;
#100;
d=1; c=1;

end

endmodule
Output Simulation Waveform:

JK Flip Flop:
 FIG: RTL Design Schematic of a JK Flip Flop circuit.

Behavioral Modeling
module jk_ff(j,k,clk,q,qn);
input  j,k,clk;
output q,qn;
reg q,qn;

initial begin
q=1'b0;
qn=1'b1;
end

always@(posedge clk)
begin
case({j,k})
{1'b0,1'b0}:begin q=q; qn=qn;end
{1'b0,1'b1}:begin q=1'b0; qn=1'b1;end
{1'b1,1'b0}:begin q=1'b1; qn=1'b0;end
{1'b1,1'b1}:begin q=~q; qn=~qn;end
endcase
end
endmodule

module jk_ff_tb_v;

// Inputs
reg j;
reg k;
reg clk;

// Outputs
wire q;
wire qn;

// Instantiate the Unit Under Test (UUT)
jk_ff uut (
.j(j),
.k(k),
.clk(clk),
.q(q),
.qn(qn)
);

initial begin
// Initialize Inputs
j = 0;
k = 0;
clk = 0;

// Wait 100 ns for global reset to finish
#100;
{j,k,clk}=3'b001; #100;
{j,k,clk}=3'b010; #100;
{j,k,clk}=3'b011; #100;
{j,k,clk}=3'b100; #100;
{j,k,clk}=3'b101; #100;
{j,k,clk}=3'b110; #100;
{j,k,clk}=3'b111; #100;