UVM: Architecture and TestBench Coding
- Verification methodology is a set of coding practice adopted by a group of people or a group of company to develop more reusable and more reliable testbench codes.
- UVM History:
- e Reuse Methodology (2002) - eRM
- Universal Reuse Methodology (2006) - URM
- Advanced Verification Methodology (2004) - AVM [Mentor Graphics]
- Open Verification Methodology (2008) - OVM [Mentor Graphics & Cadence]
- Universal Verification Methodology (2011) - UVM [Most recent methodology available by combining OVM & VMM maintained by Accellera - consortium of tools companies like Mentor Graphics, Synopsys, and Cadence]
- Reuse Verification Methodology - RVM
- Verification Methodology Manual (2004) - VMM [Combined project by Synopsys and arm]
- UVM is a library of Classes developed in System Verilog HDL.
- Its primary purpose is to define a common, reusable architecture for TestBench components.
- Advantage: Vertical and Horizontal reusability (across unit/cluster/SoC & across projects).
- Vertical reusability: same components can be used across same unit/cluster and in the final SoC
- Horizontal reusability: can be used across multiple projects.
- UVM and OVM are similar in architecture.
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