Verification Challenges (OVM / UVM)

Verification Challenges:

  • Challenges
    • Finding all bugs and fast in the design life cycle.
    • increasing complexity in design.
    • Limited time.
    • Limited Resources - Both the person and the compute.
  • Always more possible scenarios to test than available time and resource.
  • Continuous use of tools and verification process to improve.
Need for Standard Methodology:
  • Traditional methods don't scale up or enable re-use across verification for complex design.
  • Verification is increasingly becoming critical and complex:
    • Building constrained random test benches is complex and time-consuming.
    • Projects demand verification engineers to divide and conquer.
    • There is a need to speed up the overall process and increase efficiency from project to project.
What is a Verification Methodology?
  • Define a set of standards or process that enables efficient Verification.
  • Addresses the following aspects:
    • Automation
    • Abstraction
    • Re-use
    • Interoperability
    • Quality
What must a methodology provide?
  • Standard to enable re-use
    • Abstraction.
    • Project/Company/Industry-wide re-use.
  • A layered approach to enable a division of skills and development.
    • Developing verification IP.
    • Re-using and configuring existing verification IP.
    • Separation of stimulus from testbench structure.
    • Writing new code:
      • Assertions and coverage points.
      • Writing or re-using checkers.
      • Writing or re-using test cases.
  • A consistent approach.
    • Naming conventions,
    • Verification IP configuration.
      • Defining the number of agents.
      • How thay connect to the DUT.
      • Whether an agent is ACTIVE or PASSIVE.
    • Well-defined generation and simulation phases.
      • Build, connect, pre-run, run, post-run.
  • The power to find bugs fast.
    • Faster development of Testbench.
    • Good control on stimulus, observability and debug ability.
  • Vendor/tool independence
  • Verification management - Planning, progress, and completion.
History of Verification Methodologies:
FIG: Historical overview of Verification Methodologies.
  • ~1995: Several verification languages existed (SV, e, eRM, RVM, Vera).
  • UVM: Open Source, Popular.