UVM - Transaction Level Modelling

  • Grouping all the information needed to communicate between two components.
  • A class object that includes necessary information needed for communication between two components.
  • A Simple example can be a read/write transaction on a bus.
  • OVM/UVM class library has ovm_transaction / uvm_transaction defined for a base transaction.

class simple_trans extends uvm_transaction;
   rand data_t data;
   rand addr_t addr;
   rand enum {WRITE, READ} kind;
   constraints c1 {addr < 16'h2000;}

Transaction Level Modeling (TLM):
  • TLM is an approach that consists of multiple processes communicating with each other by sending transactions back and forth through channels.
e.g. [producer]>>--------->>[consumer]
  • Group all info, bit-level etc, and channel it through.
  • Abstract time
    • Reduces the number of activation of processes.
    • RTL evaluation of nets/signals vs evaluation of transactions.
  • Abstracts data
    • Form transaction objects instead of bit by bit details.
  • Abstracts function
    • Implement functionality with functions/processes rather than with real registers or circuits.
  • TLM Makes our code reusable and efficient.
  • TLM is the basis for modularity and re-use in OVM/UVM
  • It is all about communication through method calls:
    • A TLM port specifies the "API" to be used.
    • TLM export supplies the implementation of the methods.
  • Connections are between ports/exports, not components.
  • Transactions are objects.
  • Ports & exports are parameterized by the transaction type being communicated.
FIG: Understanding TLM (OVM/UVM)

TLM interfaces supported:
  • Unidirectional
    • Blocking (Tasks) - blocks till completion
      • put
      • get/peek
    • Nonblocking (Functions)
      • try_put
      • try_get/try_peek
      • write