- Constrained random, coverage-driven verification.
- configurable, flexible, test benches.
- Vertical and Horizontal re-use.
- Separation of tests/simulation from the test bench.
- Transaction-level communication (TLM).
- Layered sequential stimulus.
- Standardized messaging (turn-on and off the messaging of the component).
- Register layer (Newly added in UVM)
- Enables programming and verifying registers (reg implemented in a design) in a consistent and efficient manner.
- UVM is based on OVM 2.1.1
- The deprecated features from OVM were removed in UVM (deprecated.txt in the OVM install area).
- The URM and AVM compatibility layers were removed from UVM.
- Updates in UVM:
- Enhancements to the OVM callback facility, including a new message catching facility.
- Enhancements to the OVM objection mechanism.
- These enhancements introduce some minor backward incompatibilities to the OVM callback facility (UVM is nearly compatible with OVM).
- Other than this, it is a blind change from ovm_* to uvm_* for the whole library.
- UVM continues to evolve - 1.1 to 1.2.
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