- History:
- PCI (1992/1993) -
- 32bit / 33MHz - 133 MBPS
- 64bit / 66 MHz - 533 MBPS
- PCI-X (1999) -
- 1066 MBPS with 64bit / 133MHz
- PCI Express (2002)
- x1 - up to 1GBPS in each direction
- x16 - up to 16GBPS in each direction
- PCIe:
- High speed Serial Bus Standard used to connect peripheral device.
- Provides lower latency and higher data throughput, security and, reliability.
- Each PCIe link has direct/dedicated p-to-p connection (no sharing).
- Lower pin count and smaller footprint.
- Has more detailed error detection (CRC errors, link loss etc) and reporting mechanism.
- Packet-based transmission protocol (e.g. memory read; write is generated and transmitted over a serial lane).
- Has scalable link widths (1x, 2x, 4x, 8x, 16x, 32x) - more flexibility.
- Has scalable link speeds (2.5, 5.0 and 8.0 GT/sec): Here GT/sec means Gigatransfers per second.
- Topology:
 |
| FIG: Different components connect, communicate with each other |
- Switch: Used to expand PCIe bus (we can add maximum the switch supports).
- Bridge: Translates and converts to older versions for connection.
- Memory: To read and write by using the root complex.
- Architecture:
- Separate serial links connect every device to root complex (host).
- Supports full-duplex (both Tx and Rx at the same time) communication between any two endpoints
- Communication in packets.
- Transaction layer handles packetizing and de-packetizing (send and receive bit-by-bit).
- Packet types:
- Data packets - transfer data from memory <=> endpoint. e.g. VGA out card to connect to the monitor: data written in the memory gets displayed on to the VGA.
- Status packets - link negotiations, interrupt requests.
Comments
Post a Comment