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| This works as a Translator block with User-provided ports to AXI-Lite Protocol. |
- Write through AXI-Lite Protocol:
- User provides write data on app_wdata port.
- User provides write address on app_waddr port.
- When user enables app_wen the block writes data, through AXI-Lite block.
- After finishing the block sets up app_wdone and app_werror (if app_werror is '1' then there is an error else none) ports.
- Read through AXI-Lite Protocol:
- User provides read data address on app_raddr port.
- When user enables app_ren the block reads data, through AXI-Lite block.
- After finishing the block sets up app_rdone and app_rerror ports.
*Please check AXI-Stream (post) to refer axi stream master ports.
Verilog file for AXI-Lite Master (.v file):
-----------------------------------------------------
`timescale 1ns / 1ps
module m_axi_lite(
//SYSTEM SIGNALS
input wire aclk,
input wire aresetn, //negative reset signal
//WRITE ADDRESS CHANNEL SIGNALS
output wire [32-1:0] m_axi_awaddr,
output wire [3-1:0] m_axi_awprot,
output m_axi_awvalid,
input wire m_axi_awready,
//WRITE DATA CHANNEL SIGNALS
output wire [32-1:0] m_axi_wdata,
output wire [32/8-1:0] m_axi_wstrb,
output m_axi_wvalid,
input wire m_axi_wready,
//WRITE RESPONSE CHANNEL SIGNALS
input wire [2-1:0] m_axi_bresp,
input wire m_axi_bvalid,
output m_axi_bready,
//READ ADDRESS CHANNEL SIGNALS
output wire [32-1:0] m_axi_araddr,
output wire [3-1:0] m_axi_arprot,
output m_axi_arvalid,
input wire m_axi_arready,
//READ DATA CHANNEL SIGNALS
input wire [32-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rvalid,
output m_axi_rready,
//USER SIGNALS
input wire [32-1:0] app_waddr,
input wire [32-1:0] app_wdata,
input wire app_wen,
input wire [32-1:0] app_raddr,
input wire app_ren,
output wire [32-1:0] app_rdata,
output app_wdone,
output app_werror,
output app_rdone,
output app_rerror
);
//**********Write Channel**********//
wire waddr_chnl_done,wdata_chnl_done,wresp_slave, wresp_slave_final;
//axis to send write address
axi_stream_master axis_waddr (.areset_neg(aresetn),
.aclk(aclk),
.data (app_waddr),
.send (app_wen),
.tready (m_axi_awready),
.tvalid (m_axi_awvalid),
.tlast (m_axi_awvalid),
.tdata (m_axi_awdata),
.finish (wdata_chnl_done)
);
assign m_axi_awprot = 3'o0; //normal access be default
//axis to send write data
axi_stream_master axis_wdata(.areset_neg(aresetn),
.aclk(aclk),
.data (app_wdata),
.send (appwen),
.tready (m_axi_wready),
.tvalid (m_axi_wvalid),
.tlast (m_axi_wvalid),
.tdata (m_axi_wdata),
.finish (wdata_chnl_done)
);
assign m_axi_wstrb = (m_axi_wvalid) ? 4'b1111 : 4'b0000; //all bytes of line contain valid data
//assign m_axi_wstrb = 4'b1111; // allbytes of line contain valid data
//wresponse
wire [31:0] wchnl_resp; //this is bresp of the master. Only the last 2 bits are valid bits
//axis slave to receive write response
axis_s axis_resp (.areset_neg(aresetn),
.aclk(aclk),
.data (wchnl_resp), //channel response saved here
.ready (app_wen),//user saying slave is ready
.tready (m_axi_bready),
.tvalid (m_axi_bvalid),
.tlast (m_axi_bvalid),
tdata ({30'b0,m_axi_bresp}),
.finish (wresp_slave)
);
//Response should be Okay or ExOkay
assign wresp_slave_final = wresp_slave && (wchnl_resp [1:0] == 2'b00 || wchnl_resp [1:0] == 2'b01);
assign app_wdone = wresp_slave_final;
assign app_wdone = wresp_slave && (wchnl_resp [1:0] == 2'b10 /*slave error*/ || wchnl_resp [1:0] == 2'b11 /*decode error*/);
//**********Read Channel***********/
wire raddr_chnl_done,rdata_chnl_done;
assign m_axi_arprot = 1'b0; //normal access
//axis slave to send read address
axi_stream_master axis_raddr (.areset_neg(aresetn),
.aclk(aclk),
.data(app_raddr),
.ready (app_ren),
.tready (m_axi_arready),
.valid (m_axi_arvalid),
.tlast (m_axi_arvalid),
tdata (m_axi_araddr),
.finish (raddr_chnl_done)
);
//axis slave to send read data value
axis_slave axis_rdata (.areset_neg(aresetn),
.aclk(aclk),
.data(app_rdata),
.ready (app_ren), //user saying slave is ready
.tready (m_axi_rready),
.valid (m_axi_rvalid),
.tlast (m_axi_rvalid),
tdata (m_axi_rdata),
.finish (rdata_chnl_done)
);
//Response should be OKay or EXokay
assign app_rdone = rdata_chnl_done && (m_axi_rresp [1:0] == 2'b00 || m_axi_rresp [1:0] == 2'b01);
assign app_rerror = wresp_slave && (m_axii_rresp [1:0] == 2'b10 || m_axi_rresp [1:0] == 2'b11);
endmodule
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