TRANSISTOR LEVEL, GATE LEVEL AND BEHAVIORAL MODELLING
- Transistor level modelling:
|Fig: CMOS NOR Gate Schematic|
- Hardware is described in terms of transistor and the circuit is mapped with the program.
EXAMPLE CODE (Above circuit in system verilog):
module my_nor (output y, input a,b);
wire c; //c is an internal variable
pmos p1(c,vdd,a); //p1 and p2 are the instances of pmos
nmos n1(y,gnd,a); //n1 and n2 are the instances of nmos
- nmos (out,data,control);
- pmos (out,data,control);
|Fig: Mapped NOR circuit.|
- Gate level modelling:
- Here, the hardware is described on the Gate level.
//NOR Gate: Gate Level
module my_nor1 (output y, input a,b);
- Behavioral modelling:
- Here, we write the system verilog program or higher level language program.
- This type of modelling is important because it can be used to implement the complex circuits by describing them behavioral level.
//NOR Gate: Behavioral Modelling
module my_nor2 (output y, input a,b);
assign y=(a ~| b);
You wrote this post very carefully. The amount of information is stunning and also a gainful article for us. Keep sharing this kind of articles, Thank you.Chip Layout TrainingReplyDelete